The present invention generally relates to non-volatile semiconductor memory devices, and more particularly to a cell array of such devices wherein each device comprises an erasable and programmable read only memory device having a floating gate and a control gate.
FIG. 1 shows a conventional erasable and programmable read only memory (EPROM) disclosed in U.S. Pat. No. 4,893,705 or Japanese Laid-Open Patent Publication No. 56-130975 (which corresponds to U.S. patent application Ser. No. 88,789 filed on Oct. 29, 1979). Active regions of a plurality of EPROM cells T11, T12, T21 and T22 are electrically coupled through a bulk interconnection line. The EPROM cells T11, T12, T21 and T22 are arranged as follows. Selective oxide films (field insulation (oxidation) films) 1b having rectangular plans are formed on a top surface of a semiconductor substrate 1a and spaced apart from each other so that the field insulation films 1b are arranged in a matrix. Regions surrounded by the field insulation films 1b are arranged in a grid and serve as element formation regions 1c. Floating gate electrodes 1e are formed at a center part of belt-shaped portions 1d. An insulating film is formed on the entire surface including the floating gate electrodes 1e, and control gate electrodes 1f are formed on the insulating film so that the control gate electrodes 1f overlap with the floating gate electrodes 1e. Active regions 1g are formed on both sides of the gate electrodes 1e and 1f by a self-alignment process.
The active regions 1g are integrally formed in X-shaped regions of the element formation regions 1c so that the EPROM cells T11, T12, T21 and T22 are coupled. The control gate electrodes 1f are formed at an angle of about 45.degree. with respect to the direction in which the belt-shaped portions 1d run, and arranged so that the control gate electrodes 1f run above the floating gate electrodes 1e. The floating gate electrodes 1e and the control gate electrodes 1f have belt-shaped portions so that they are orthogonal to the belt-shaped portions 1d.
An interlayer insulating film (not shown) is formed on the control gate electrodes 1f. Contact holes 1h are formed at positions of the interlayer insulating film which correspond to the center portions of the X-shaped portions of the active regions 1g. Bit lines BL, which are formed on the interlayer insulating film, are formed so that the bit lines BL are electrically in contact with the active regions 1g through the contact holes 1h.
A device including the EPROM cells T11, T12, T21 and T22 has an equivalent circuit shown in FIG. 2. For example, when the cell T22 is selected, a signal is applied to the control gate electrode 1f of the cell T22 via a word line WL2, and signals are applied to the two active regions 1g through bit lines BL2 and BL3.
The floating gate electrodes 1e and the control gate electrodes 1f are formed as follows. Referring to FIG. 3A, a first polysilicon film 1i provided for forming the floating gate electrodes 1e is formed on the entire surface. Next, the first polysilicon film 1i is patterned so that patterned portions run parallel to the bit lines BL, that is, the patterned portions are inclined at approximately 45.degree. with respect to the long-side directions of the belt-shaped portions 1d in which the long-side edges thereof run.
As shown in FIG. 3B, a second polysilicon film 1j, provided for forming the control gate electrodes 1f, is formed on the entire surface including the interlayer insulating film. After that, as shown in FIG. 3C, the first and second polysilicon films 1i and 1j are patterned. Thereby, the floating gate electrodes 1e and the control gate electrodes 1f are formed so that they have no positional error in the width direction thereof.
It should be noted that the ends of the floating gate electrodes 1e are close to the belt-shaped portions 1d of the element formation regions 1c. If a patterning error occurs during the step in which the first polysilicon film 1i is patterned, as shown in FIG. 4A, one of the two ends of the floating gate electrode 1e is positioned above the belt-shaped portion 1d and the floating gate electrode 1f is positioned above the belt-shaped portion 1d. Thus, as shown in FIG. 4B, the control gate electrode 1f has a portion which does not overlap with the floating gate electrode 1e.
As is well known, the threshold voltage of the EPROM cell transistor varies due to the existence/non-existence of a charge stored in the floating gate electrode 1e of the transistor. This variation in the threshold voltage is used for storing information. For example, when the floating gate electrode 1e is electrified so that it has a negative polarity, a channel is not formed in the semiconductor substrate 1a even if a predetermined voltage is applied to the control gate electrode 1f. Thus, no current passes between the active regions 1a located on both sides of the floating gate electrode 1e, so that the transistor is maintained in the OFF state. In this way, data is written into the EPROM cell.
On the other hand, when the floating gate electrode 1e is not electrified, the electric field caused by applying a voltage to the control gate electrode 1f is not reduced by the floating gate electrode 1e. Thus, a channel is formed under the floating gate electrode 1e, so that a current passes between the active regions 1g located on both sides of the floating gate electrode 1e. In this way, no data is written into the EPROM cell.
In the case where the control gate electrode 1f positionally deviates from the floating gate electrode 1d with respect to the belt-shaped portion 1d, the electric field formed by the control gate electrode 1f directly affects the semiconductor substrate 1a. The above-mentioned positional deviation of the floating gate electrode 1e forms a portion which cannot prevent the formation of the channel. This increases errors in readout data.